Data security

ABSTRACT

This document discloses data security systems and methods of securing data. A cache memory can be connected between a decryption engine and a central processing unit (“CPU”) to increase security of encrypted data that is stored in a datastore. The decryption engine can retrieve the encrypted data from the datastore, decrypt the data, and store the decrypted data in the cache. In turn, the decrypted data can be accessed by the CPU. The data can be encrypted with a secret key, so that decryption can be performed with the secret key. The key can be varied based on a memory address associated with the data. The key can be protected by restricting direct access to the decryption engine by the CPU.

BACKGROUND

This specification relates to data security.

Devices are being used to store more information electronically. Some of the data being stored is sensitive data. For example, medical records and financial information can be stored in devices to increase accessibility to the information by authorized users. The sensitivity of the data being stored can be considered when determining the type of device and security measures that are implemented to protect the data.

An example device that is used to store information electronically is a Smart card. Smart cards can store information in memory that is embedded in the card. The memory can be used to store sensitive data, such as financial information, medical records, identification information, as well as other sensitive data. Once the memory is stored in the memory of the Smart card, the card can be read by computing devices that are equipped with peripherals that can interface with the Smart cards. Encryption techniques can be used to increase the security of sensitive data in Smart cards

Encryption techniques can, for example, transform data based on an encryption key to prevent access to the data without a valid decryption key. However, if unauthorized users obtain the decryption key then the security of the data can be compromised.

SUMMARY

This document discloses data security systems and methods of securing data. Cache memory (e.g., Random Access Memory (“RAM”)) can be connected between a decryption engine and a central processing unit (“CPU”) to increase security of encrypted data that is stored in a datastore. The decryption engine can retrieve the encrypted data from the datastore, decrypt the data, and store the decrypted data in the cache memory. In turn, the decrypted data can be accessed by the CPU. The data can be encrypted and decrypted with a secret key. The key can be varied based on a memory address associated with the data. The key can be protected by restricting direct access to the decryption engine by the CPU.

Particular implementations of the subject matter described in this specification can be implemented so as to realize one or more of the following advantages. A secret key can be used to enhance data security (e.g., symmetric block ciphers). The secret key can be varied based on a memory address associated with the data. Encrypted data can be identified based on its memory location, thereby resulting in reduced memory overhead. Access to encrypted data can be restricted. Decryption speed can be increased over that realized using a public key. Increased security can be provided for Smart cards and other devices that store sensitive data.

The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of an example environment in which data security devices, systems, and methods can be implemented.

FIG. 2 is a block diagram of an example data management system.

FIG. 3 is a flow chart of an example process of securing data.

FIG. 4 is a flow chart of an example process of managing memory.

Like reference numbers and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION

This document discloses devices, systems, and methods that increase data security capabilities while decreasing memory access times and memory overhead. A system can be implemented with a cache that is connected between a decryption engine and a CPU. A controller can define a portion of a datastore as a memory window. The memory window can be segmented into memory blocks, each memory block having a defined number of bytes. One or more memory blocks can define a sub-window of memory.

When the CPU requests encrypted data, the controller can, for example, retrieve the memory block containing the data and pass the memory block to the decryption engine. The decryption engine can decrypt the memory block and store the decrypted memory block in the cache. In turn, the CPU can retrieve the portion of the decrypted memory block containing the requested data from the cache.

The decrypted memory block can be maintained in the cache until the CPU requests data that is not maintained in the cache. Therefore, if the CPU requests additional data that are maintained in the cache, the CPU can continue to access the data from the cache without waiting for the memory block to be decrypted. The access time of the cache can be faster than that of the datastore. Therefore, the CPU can execute data from the cache faster than the CPU can retrieve data from the datastore, decrypt the data, and execute the data from the cache.

In addition to faster access times, the cache architecture can also increase data security. Stronger encryption methods (e.g., TDES) can be used because larger portions of data (e.g., 16 bytes rather than 1 byte) can be retrieved from the datastore with each fetch. Additionally, the decryption key can be varied for each memory block based, in part, on the sub-window address associated with the memory block.

§1.0 Example Data Security Environment

FIG. 1 is a diagram of an example environment in which data security devices, systems, and methods can be implemented. A Smart card 102 is a card device that can include an embedded integrated circuit chip 103. The integrated circuit chip can include a memory structure, or a secure microcontroller that includes a memory structure, that can operate as a datastore 104. The datastore 104 of the Smart card 102 can store digital information that can be accessed by a computing device 106 that is in communication with the Smart card 102. The computing device 106 can communicate with the Smart card 102 through direct contact with the Smart card 102, or over a wireless connection.

The computing device 106 can be equipped with an interface peripheral 108 (e.g., Smart card reader) to facilitate direct contact with the Smart card 102. A Smart card user 110 can insert the Smart card 102 into the interface peripheral 108. Once the Smart card 102 is inserted, the interface peripheral 108 can make contact with the integrated circuit chip 103. In turn, the computing device 106 can access the datastore 104 or communicate with the microcontroller to store and retrieve data from the datastore 104. Interface peripherals can also have wireless capabilities that facilitate wireless communication with the Smart card 102.

Smart cards 102 can be used in applications that require security to protect the data that is stored on the Smart card 102. For example, Smart cards 102 can be used as credit/debit cards, to store sensitive healthcare data, and to access secure buildings. Therefore, it may be advantageous to prevent unauthorized access to the information stored in the datastore 104. Encryption can be used to protect the data stored in the datastore 104. Encryption can prevent unauthorized access to data, for example, by transforming the data based on an encryption key. In turn, the original data cannot be read without a valid decryption key. Therefore, encrypting data can increase the security of the data.

In some implementations, a data security subsystem 112 can be coupled to the datastore 104 to increase the security of data stored in the datastore 104 and facilitate efficient data management. For example, the data security subsystem 112 can encrypt data that is stored in the datastore 104 to increase the security of the data. Encrypted data is decrypted before it can be executed or otherwise used.

Additionally, the data security subsystem 112 can be operable to define portions of the datastore 104 as memory windows for encrypted data storage to facilitate more efficient memory management. For example, the data security subsystem 112 can identify data as encrypted data based on the data being stored in the memory window of the datastore 104. Therefore, an encryption flag is not required to identify encrypted data.

Identifying data as encrypted based on being stored in the memory window can facilitate more efficient memory use because memory is not required to store the encryption flag. An encryption flag can be a data value that identifies corresponding data as encrypted. The encryption flag can be stored, for example, at a memory location that is associated with the corresponding encrypted data. Identifying encrypted data without the use of an encryption flag can facilitate more efficient use of memory resources because the memory that would be used to store the encryption flag can be used to store additional program instructions or other data.

Data security can also be enhanced based on the architecture of the data security subsystem 112. For example, the data security subsystem 112 can be implemented to restrict access to encrypted data and keys that are used to encrypt/decrypt data in the datastore 104, as discussed below.

§2.0 Example Data Management System

FIG. 2 is a block diagram of an example data management system 200. In some implementations, the data management system 200 can include a datastore 104, a data security subsystem 112, and a CPU 204. The data management system 200 can be implemented, for example, on a Smart card (e.g., Smart card 102 of FIG. 1) or any other device, or system, in which data is secured. The datastore 104 can be implemented, for example, as RAM, read only memory (“ROM”), programmable read only memory (“PROM”), or other suitable memory structures. The CPU 204 can be implemented, for example, as a computer processor, a microcontroller, or any other processing device that can be included on a Smart card (e.g., Smart card 102 of FIG. 1). The data security subsystem 112 can be operable to receive data requests from the CPU 204 and manage access to the data stored in the datastore 104 in response to the requests.

In some implementations, the security subsystem 112 can define a memory window 206 in the datastore 104. The memory window 206 can be a portion of the datastore 104 in which encrypted data can be stored. The data security subsystem 112 can define the memory window 206, for example, based on a start memory address and an end memory address or any other allocation scheme.

The security subsystem 112 can further define one or more memory blocks 208 in the memory window 206. Each memory block 208 can include, for example, 16 bytes of memory. The length of the memory blocks can be based on the length of an encryption key that is used to secure the data, or otherwise on the application. One or more memory blocks can define a memory sub-window. Each memory sub-window can have a corresponding sub-window address that can be used to facilitate encryption/decryption key variation, as discussed below.

In some implementations, the memory window 206 can be used exclusively to store encrypted data. In these implementations, encrypted data can be identified by its memory address rather than an encryption flag. For example, data that is stored at a memory address located within the memory window 206 (e.g., between the start memory address and the end memory address) can be identified as encrypted data. While the memory window 206 is presented as a contiguous set of memory blocks, the memory window 206 can be defined by non-contiguous memory addresses.

§2.1 Example Security Subsystem Encryption/Decryption

In some implementations, the data security subsystem 112 can include a controller 210, a decryption engine 212, and a cache 214. The data security subsystem 112 can also include a cipher management engine 218. The data security subsystem 112 can be coupled to the datastore 104 to manage access to data stored in the datastore 104 by the CPU 204.

In some implementations, the controller 210 can store encrypted data exclusively in the memory window 206. For example, when the controller 210 receives encrypted data, the controller 210 can store the encrypted data in a memory block 208 that has an address within the memory window 206. However, when the controller 210 receives data that is not encrypted, the controller 210 can store the unencrypted data to a memory block 209 that has an address outside the memory window 206.

The data security subsystem 112 can receive a data request (e.g., instruction fetch) from the CPU 204. In response to the request, the controller 210 can retrieve the requested data from the datastore 104. In some implementations, the controller 210 can retrieve a block of data stored in a memory block 208 that contains the data requested by the CPU 204, rather than the portion of the block of data requested. For example, if the requested data corresponds to 1 byte of data in a 16 byte block of memory, the controller 210 can retrieve the entire 16 byte block of data stored in the 16 byte block of memory, rather than just the single byte of data requested by the CPU 204. The controller 210 can pass retrieved data to the decryption engine 212 if the retrieved data is encrypted or to the cache 214 if the retrieved data is not encrypted.

In some implementations, the controller 210 can determine whether the retrieved data is encrypted based on an address associated with the retrieved data. For example, the controller 210 can identify the memory address associated with the retrieved data. If the memory address corresponds to an address that is included in the memory window 206, then the controller 210 can determine that the data is encrypted. If the memory address does not correspond to an address that is included in the memory window 206, the controller 210 can determine that the data is not encrypted. In turn, if the controller determines that the retrieved data is encrypted, the controller 210 can pass the data to the decryption engine 212. If the controller 210 determines that the retrieved data is not encrypted, the controller 210 can pass the retrieved data directly to the cache 214.

The decryption engine 212 can receive encrypted data from the controller 210 and decrypt the data using a decryption key. In some implementations, the decryption key can be a secret key, rather than a public key. A secret key is an encryption key that is not publicly available, for example, through a certificate authority. A secret key can be initialized in a device, for example, during manufacturing. When a secret key is used to encrypt data, the same secret key must be used to decrypt the data. Therefore, only devices having access to (e.g., initialized with) the secret key can be used to decrypt the data.

Because the secret key is resident in devices that are authorized to access data encrypted with the secret key, these devices are not required to access, for example, a certificate authority to obtain the key. Therefore, decryption can be performed more quickly with secret keys than public keys. In turn, data encrypted with a secret key can be accessed by authorized devices more quickly than data encrypted with public keys.

The strength of an encryption/decryption key can depend, in part, on the length of the key used. However, the length of the key that can be used can depend, in part, on the size of the data that is encrypted. For example, 16 bytes of data can be encrypted with a longer key than 1 byte of data. Therefore, the encryption algorithm used to encrypt 16 bytes of data using the longer key can be stronger than the encryption algorithm used to encrypt 1 byte of data. In some implementations, memory blocks 208 can be defined to have a length that corresponds to the encryption/decryption algorithm to be used to secure the data.

A symmetric block cipher key is an example of a key that can be used to encrypt a 16 byte block of data. The symmetric block cipher can be a cipher that conforms to the data encryption standard (DES), triple data encryption standard (Triple-DES), or advanced encryption standard (AES).

In some implementations, the security subsystem 112 can include a cipher management engine 218. The cipher management engine 218 can generate a key that is varied from a base secret key according to the location to which data is stored within the memory window 206. The key can be derived, for example, by applying a function to the base secret key and the address associated with the data location in the memory window 206. When the encrypted data is retrieved by the controller 210 and passed to the decryption engine 212 to be decrypted with a decryption algorithm. The decryption algorithm uses the same key that was used to encrypt the data. The decryption key can be retrieved, for example, from the cipher management engine 218. In turn, the decryption engine 212 can use the decryption key to decrypt the data. In some implementations, the decryption engine 212 can be operable to determine the decryption key based on the function and the sub-window address.

Once the data retrieved from the block of memory 208 have been decrypted, the decrypted block of data is stored in the cache 214. The cache 214 can be a volatile memory that is accessible by the CPU 204. For example, the cache 214 can be a RAM memory structure. Once the decrypted data is available in the cache 214, the CPU 204 can retrieve the decrypted data that it requested from the cache 214.

In some implementations, the cache 214 can maintain the decrypted data until the CPU requests data that is stored in another block of memory 208. For example, if a first data request from the CPU 204 requests a byte of data that is located in block 0, then the encrypted data stored in block 0 can be decrypted, as described above, and stored in the cache 214 for access by the CPU 204. If a second data request from the CPU 204 requests another byte of data that is located in block 0, then the cache 214 can maintain the decrypted data. Thus, the data in block 0 does not need to be decrypted again and the CPU 204 can directly access the decrypted data in cache 214. However, if the second data request from the CPU 204 requests data that is located in a block of memory 208 other than block 0 (e.g., block 1), then the data from block 1 can be retrieved and decrypted as described above. In this situation, the cache 214 can discard the decrypted data from block 0 in response to the second data request.

Maintaining the decrypted data in the cache 214 until data from another memory block 208 is requested can increase data access time. The access times associated with the cache 214 are generally faster than those associated with the datastore 104. Therefore, operations can be executed more quickly from the cache 214 than the datastore 104. Additionally, maintaining the decrypted data in the cache 214 enables access to the data without waiting for the decryption process to be performed. This can further increase access time to data that has been decrypted and is maintained in the cache 214.

§2.2 Example Architecture Based Security

In some implementations, the architecture of the data management system 200 can enhance data security. FIG. 2 illustrates an example architecture for the data management system 200 that can be used to increase data security. As shown in FIG. 2, the CPU 204 is connected to the cache 214. However, CPU 204 is independent of (e.g., not connected to, or in direct communication with) the datastore 104, the decryption engine 212, or the cipher management engine 218.

In some implementations, connecting the CPU 204 to the cache 214 can increase security of encrypted data. When CPU 204 is connected to the cache 214 the CPU 204 can be limited to executing instructions maintained in the cache 214. Therefore, the CPU 204 cannot execute data directly from the memory store 104. Accordingly, the CPU 204 cannot download an entire program from the datastore 104. Similarly, the CPU 204 cannot use the encrypted version of the data and the unencrypted version of the data to determine the encryption key. Thus, incorporating a cache 214 between the datastore 104 and the CPU 204 facilitates increased data security.

In some implementations, the CPU 204 can be implemented independent of the decryption engine 212. In these implementations, CPU 204 access to the decryption engine can be restricted and the controller 210 can independently manage data decryption. By restricting access to the decryption engine 212, the CPU 204 cannot identify the secret key by accessing the decryption engine 212. Similarly, the CPU 204 cannot learn the function that is used to vary the secret key by accessing the decryption engine 212. Additionally, because the decryption engine 212 is independent of the CPU 204, the CPU 204 cannot disable decryption. Therefore, the CPU 204 cannot gain access to the encrypted data through the cache 214.

§3.0 Example Process Flow

FIG. 3 is a flow chart of an example process 300 of securing data. The process 300 can be implemented, for example, in the security subsystem 112 and/or data management system 200.

Stage 302 receives a first data fetch instruction. In some implementations, the first data fetch instruction can be a request for data that is stored in a datastore. The first data fetch instruction can be received from a computing device (e.g., computer, server, CPU, etc). The first data fetch instruction can be received, for example, by the security subsystem 112.

Stage 304 retrieves data in response to the fetch instruction. The data can be located, for example, in a memory sub-window. The block of data can be encrypted with a cipher that is based on a memory sub-window address and a secret key. The cipher can satisfy, for example, a data encryption standard, a triple data encryption standard, or an advanced encryption standard block cipher. The data can be retrieved, for example, by the controller 210.

Stage 306 determines whether the retrieved data is stored in a predefined memory window. In some implementations, data stored in the predefined memory window is encrypted. The predefined memory window can be defined by a start memory address and an end memory address. Encrypted data can be stored exclusively in the predefined memory window. If the data is not stored in the predefined memory window, then the process 300 can continue to stage 310. If the data is stored in the predefined memory window, then the process can continue to stage 308.

Stage 308 decrypts the retrieved data with a cipher. In some implementations, the cipher can be based on the sub-window address of the data and a secret key. The data can be decrypted, for example, by the decryption engine 212.

Stage 310 provides access to the decrypted data in a memory cache. In some implementations, the memory cache is independent of the predefined memory window. Access to the data can be provided, for example, by the cache 214.

Stage 312 receives a second data fetch instruction. In some implementations, the second fetch instruction can be a request for data that is stored in a datastore. The second data fetch instruction can be received from a computing device. The second data fetch instruction can be received, for example, by the security subsystem 112.

Stage 314 determines whether the data requested by the second data fetch instruction is in the memory cache. If the requested data is in the memory cache, the process 300 can continue to stage 310. If the requested data is not in the memory cache, the process 300 can continue to stage 304.

FIG. 4 is a flow chart of an example process 400 of managing memory. The process 400 can be implemented, for example, in the security subsystem 112 and/or data management system 200.

Stage 402 defines an encrypted data memory window in a datastore. In some implementations, the memory window can be used to store encrypted data. The memory window can be defined, for example, by the controller 210.

Stage 404 defines at least one memory sub-window in the memory sub-window. In some implementations, each memory sub-window can include one or more memory blocks. Each memory block can have a length that is defined by a length of an encryption data size used to encrypt the data stored in the memory block. The memory sub-window can be defined, for example, by the controller 210.

Stage 406 stores encrypted data in the memory window. In some implementations, the encrypted data can be encrypted with an encryption key that is based on a memory sub-window address. The memory sub-window address can correspond to the memory location to which the data is stored. Data can be identified as being encrypted based on being stored in the memory window. The encrypted data can be stored in the memory window, for example, by the controller 210.

While this document contains many specific implementation details, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Similarly, while process steps are depicted in the drawings in a particular order, this should not be understood as requiring that such process steps be performed in the particular order shown or in sequential order, or that all illustrated process steps be performed, to achieve desirable results.

Particular embodiments of the subject matter described in this specification have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. 

1. A method of securing data, comprising: receiving a first data fetch instruction; retrieving data from a predefined memory window in response to the first data fetch instruction, wherein the data is encrypted with a cipher that is based on a memory sub-window address and a secret key; decrypting the retrieved data with the cipher; providing access to the decrypted data in a memory cache that is independent of the predefined memory window; and maintaining the decrypted data in the memory cache until a second data fetch instruction that requests an instruction that is not maintained in the memory cache is received.
 2. The method of claim 1, wherein the predefined memory window is a portion of a memory structure defined based on a start memory address and an end memory address and encrypted data is stored exclusively in the predefined memory window.
 3. The method of claim 1, wherein the memory sub-window comprises one or more memory blocks in the predefined memory window.
 4. The method of claim 3, further comprising: receiving data that is encrypted based on an address of the memory sub-window to which the data is to be stored and the secret key; and storing the encrypted data to a memory block in the memory sub-window.
 5. The method of claim 1, wherein the predefined memory window is defined in a non-volatile memory structure.
 6. The method of claim 1, wherein the predefined memory window comprises a portion of a Smart card memory.
 7. The method of claim 1, wherein the cipher comprises a data encryption standard, a triple data encryption standard, or an advanced encryption standard block cipher.
 8. A data security system, comprising: a central processing unit; a first datastore comprising a memory window defined in a memory structure, wherein the memory window comprises a portion of memory that is defined by a start address and an end address; a decryption engine coupled to the memory structure to decrypt data retrieved from the memory window with a cipher that is based on a memory sub-window address and a secret key; and a second datastore comprising a memory cache coupled to the decryption engine and the central processing unit, the second datastore operable to store the decrypted data for execution by the central processing unit, wherein the memory cache stores the decrypted data until the central processing unit requests data that is not stored in the second datastore.
 9. The data security system of claim 8, further comprising a cipher management engine to generate a cipher for a memory sub-window based on the memory sub-window address and the secret key, wherein the key management engine is operable to generate a unique decryption cipher for each memory sub-window.
 10. The data security system of claim 8, further comprising a controller operable to retrieve encrypted data from the first datastore, provide the encrypted data to the decryption engine, and initiate decryption of the encrypted data by the decryption engine.
 11. The data security system of claim 10, wherein the controller is further operable to define the start address and the end address of the predefined memory window.
 12. The data security system of claim 8, wherein the memory cache is operable to protect the decrypted data from access through a read operation initiated by the central processing unit.
 13. The data security system of claim 8, wherein the first datastore, the decryption engine, and the second datastore are implemented on a Smart card.
 14. A data security device comprising: means for retrieving data from a predefined memory window in response to a first fetch instruction received from a central processing unit, wherein the data is encrypted with a cipher that is based on a memory sub-window address and a secret key; means for decrypting the retrieved data using the cipher, wherein the decrypting is performed by a decryption engine that is independent of the central processing unit; means for providing access to the decrypted data in a memory cache that is independent of the predefined memory window; and means for maintaining the decrypted data in the memory cache until a second fetch instruction that requests an instruction that is not maintained in the memory cache is received.
 15. A method, comprising: defining a memory window in a datastore to store encrypted data; defining at least one memory sub-window comprising one or more memory blocks of the memory window; and storing encrypted data in the memory sub-window, wherein the encrypted data is encrypted with an encryption key that is based on the memory sub-window address that corresponds to a memory location to which the data is stored.
 16. The method of claim 15, further comprising defining memory blocks in the memory window, wherein each memory block has a length that is based on a length of the encryption data size.
 17. The method of claim 16, wherein the encrypted data is encrypted with a symmetric block cipher.
 18. The method of claim 15, wherein the encrypted data is identified as encrypted based on the encrypted data being stored at an address within the encrypted data memory window. 